Look up another CVE · open CVE-2026-53374 in the interactive tracker
CVE-2026-53374
drm/amdgpu: zero-initialize GART table on allocation
Published 2026-07-19 (3 months ago) by the Linux kernel CNA. Subsystem drivers/gpu. Debian urgency: not yet assigned.
What to do, per Debian release
Debian's own status for CVE-2026-53374 in every release this site tracks, and what each one means in practice. Every status below is the one the Debian Security Team publishes for this CVE. source
| Release | Status | Version | What this means |
|---|---|---|---|
| Debian 12bookworm | fixed | 6.1.176-1 | Update the kernel and reboot. Fixed in 6.1.176-1. A running kernel keeps the old code until the machine restarts. |
| Debian 13trixie | fixed | 6.12.90-1 | Update the kernel and reboot. Fixed in 6.12.90-1. A running kernel keeps the old code until the machine restarts. |
| Debian 14forky | fixed | 7.0.9-1 | Update the kernel and reboot. Fixed in 7.0.9-1. A running kernel keeps the old code until the machine restarts. |
| Debian unstablesid | fixed | 7.0.9-1 | Update the kernel and reboot. Fixed in 7.0.9-1. A running kernel keeps the old code until the machine restarts. |
The vulnerability
What the bug is
GART TLB is flushed after unmapping but not after mapping. Since amdgpu_bo_create_kernel() does not zero-initialize the buffer, when a single PTE is written the TLB may speculatively load other uninitialized entries from the same cacheline. Those garbage entries can appear valid, and a subsequent write to another PTE in the same cacheline may cause the GPU to use a stale garbage PTE from the TLB. Fix this by calling memset_io() to zero-initialize the GART table with gart_pte_flags immediately after allocation. Using AMDGPU_GEM_CREATE_VRAM_CLEARED, SDMA-based clear will not work since SDMA needs GART to be initialized to work. (cherry picked from commit d9af8263b82b6eaa60c5718e0c6631c5037e4b24)
Where it lives
The fix touches these files. If the subsystem is one you do not use, the practical exposure is lower, though the package is still the vulnerable one.
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
- What this is
- RADEON and AMDGPU DRM DRIVERSMAINTAINERS section matched on drivers/gpu/drm/amd/ · amd-gfx@lists.freedesktop.org · Supported
- Kernel module
- amdgpu
Check it on the machine
grep -w CONFIG_DRM_AMDGPU /boot/config-$(uname -r)Reads the booted kernel's own configuration, on the machine and nowhere else. =y is built in, =m is a module, and an is not set line means the code is not there.
lsmod | grep -w amdgpuPrints a line if that module is loaded right now, and nothing if it is not. One that is not loaded can still be loaded later by anything that needs it.
Show whether Debian builds this, per release
Debian builds this, but not on every flavour. At least one release below builds the code on some of its kernel flavours and not on others, so the answer depends on the architecture and flavour installed.
- bookwormMnot built on amd64/cloud-amd64, arm64/cloud-arm64, armhf/armmp, armhf/armmp-lpae, armhf/rt/armmp
- trixieMnot built on amd64/cloud-amd64, arm64/cloud-arm64, armel/rpi, armhf/armmp, armhf/armmp-lpae, armhf/rt/armmp, s390x/s390x
- forky, sidMnot built on amd64/cloud-amd64, arm64/cloud-arm64, s390x/s390x
- M
- a module where it is built at all; some flavours do not build it
- Build switch
- CONFIG_DRM_AMDGPU
From the configuration Debian publishes for every kernel flavour it builds. It covers only the architectures Debian ships a linux-config package for, and nothing about a kernel you built yourself. Debian's own status above stays authoritative about the source package.MAINTAINERS kbuild Makefiles Debian linux-config packages
Signals
- Published
- 2026-07-19 (3 months ago)source
- CVSS
- 8.8 high
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:Hsource recompute it - Attack vector
- local (AV:L)source
- EPSS
- 0.13%, higher than 2.1% of all CVEssource
- CISA KEV
- not listedthe KEV catalogue
- Debian urgency
- not yet assignedsource
- Subsystem
- drivers/gpu
Upstream fixes
The versions the CNA records as introducing and fixing this, and the commit for each. source
| Introduced | Fixed in | Commit |
|---|---|---|
| 4.2 | 6.1.175 | 40df11255d71 |
| 4.2 | 6.6.140 | 91fbb5e635c8 |
| 4.2 | 6.12.90 | 8ae8b9e74bab |
| 4.2 | 6.18.32 | b17175d0a375 |
| 4.2 | 7.0.9 | 791941be5da1 |
| 4.2 | 7.1 | e6c2e6c2e1fa |
Why the CNA scored it this way
Quoted from the kernel CNA's own scoring file, word for word. A highlighted metric carries the most severe value CVSS v3.1 defines for it, which is what pushes the score up. source
- AV:LAttack vector, local
- The bug is reached when a local process with access to /dev/dri/renderD* issues AMDGPU DRM ioctls (GEM_CREATE, CS) that bind GTT buffers through amdgpu_ttm_backend_bind() → amdgpu_gart_bind(), writing GART PTEs without a TLB flush. This is a local GPU driver ioctl path, not a network protocol.
- AC:LAttack complexity, low
- An attacker with render-node access can reliably trigger GART PTE writes by allocating and binding GTT-domain buffers via standard ioctls; they control mapping timing and concurrency. Uninitialized VRAM contents at driver init are not an attacker-uncontrollable gate for triggering the stale-TLB condition.
- PR:LPrivileges required, low
- All AMDGPU GEM/CS ioctls require DRM_AUTH|DRM_RENDER_ALLOW, which is satisfied by membership in the render/video group on typical desktop, workstation, and cloud-GPU instances—not real root in the init namespace.
- UI:NUser interaction, none
- Exploitation requires only programmatic ioctl and GPU command submission; no victim interaction such as opening files or mounting filesystems is needed beyond the attacker already having render-node access.
- S:CScope, changed
- Stale garbage GART PTEs in the GPU TLB can cause the GPU to DMA to/from arbitrary physical pages outside the driver's intended mappings, bypassing the GART/IOMMU address-translation boundary that is supposed to confine GPU memory access.
- C:HConfidentiality impact, high
- Speculatively loaded garbage PTEs that appear valid can redirect GPU reads to unintended physical memory, including kernel and other processes' pages, constituting arbitrary memory disclosure via rogue DMA.
- I:HIntegrity impact, high
- Those same stale valid PTEs can redirect GPU writes to arbitrary physical addresses, enabling arbitrary memory corruption and potential code execution through DMA write primitives.
- A:HAvailability impact, high
- GPU DMA through invalid or garbage PTEs to unintended physical addresses can cause IOMMU faults, machine checks, GPU hangs, or kernel oops/panic, producing full system availability loss.