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CVE-2026-53354
arm64: errata: Mitigate TLBI errata on various Arm CPUs
Published 2026-07-01 (4 months ago) by the Linux kernel CNA. Subsystem Documentation/arch. Debian urgency: not yet assigned.
What to do, per Debian release
Debian's own status for CVE-2026-53354 in every release this site tracks, and what each one means in practice. Every status below is the one the Debian Security Team publishes for this CVE. source
| Release | Status | Version | What this means |
|---|---|---|---|
| Debian 12bookworm | fixedDLA-4665-1 · 2026-07-03 · text | 6.1.176-1 | Update the kernel and reboot. DLA-4665-1 shipped the fix on 2026-07-03, in 6.1.176-1. A running kernel keeps the old code until the machine restarts. |
| Debian 13trixie | fixed | 6.12.94-1 | Update the kernel and reboot. Fixed in 6.12.94-1. A running kernel keeps the old code until the machine restarts. |
| Debian 14forky | fixed | 7.0.13-1 | Update the kernel and reboot. Fixed in 7.0.13-1. A running kernel keeps the old code until the machine restarts. |
| Debian unstablesid | fixed | 7.0.13-1 | Update the kernel and reboot. Fixed in 7.0.13-1. A running kernel keeps the old code until the machine restarts. |
The vulnerability
What the bug is
A number of CPUs developed by Arm suffer from errata whereby a broadcast TLBI;DSB sequence may complete before the global observation of writes which are translated by an affected TLB entry. These errata ONLY affect the completion of memory accesses which have been translated by an invalidated TLB entry, and these errata DO NOT affect the actual invalidation of TLB entries. TLB entries are removed correctly. This issue has been assigned CVE ID CVE-2025-10263. To mitigate this issue, Arm recommends that software follows any affected TLBI;DSB sequence with an additional TLBI;DSB, which will ensure that all memory write effects affected by the first TLBI have been globally observed. The additional TLBI can use any operation that is broadcast to affected CPUs, and the additional DSB can use any option that is sufficient to complete the additional TLBI. The ARM64_WORKAROUND_REPEAT_TLBI workaround is sufficient to mitigate the issue. Enable this workaround for affected CPUs, and update the silicon errata documentation accordingly. Note that due to the manner in which Arm develops IP and tracks errata, some CPUs share a common erratum number.
Where it lives
The fix touches these files. If the subsystem is one you do not use, the practical exposure is lower, though the package is still the vulnerable one.
Documentation/arch/arm64/silicon-errata.rst
arch/arm64/Kconfig
arch/arm64/kernel/cpu_errata.c
- What this is
- ARM64 PORT (AARCH64 ARCHITECTURE)MAINTAINERS section matched on Documentation/arch/arm64/ · linux-arm-kernel@lists.infradead.org · Maintained
Show whether Debian builds this, per release
Debian builds this code. Every release below compiles the affected file into the kernels it ships.
- bookworm, trixie, forky, sidy
- y
- built into the kernel image on every flavour - only a patch removes it
From the configuration Debian publishes for every kernel flavour it builds. It covers only the architectures Debian ships a linux-config package for, and nothing about a kernel you built yourself. Debian's own status above stays authoritative about the source package.MAINTAINERS Debian linux-config packages
Signals
- Published
- 2026-07-01 (4 months ago)source
- CVSS
- 8.8 high
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:C/C:H/I:H/A:Hsource recompute it - Attack vector
- local (AV:L)source
- EPSS
- 0.13%, higher than 2.3% of all CVEssource
- CISA KEV
- not listedthe KEV catalogue
- Debian urgency
- not yet assignedsource
- Subsystem
- Documentation/arch
Upstream fixes
The versions the CNA records as introducing and fixing this, and the commit for each. source
| Introduced | Fixed in | Commit |
|---|---|---|
| 3.7 | 5.10.259 | 925058203229 |
| 3.7 | 5.15.210 | 8364384ae82f |
| 3.7 | 6.1.176 | 7c3ad9365079 |
| 3.7 | 6.6.143 | e717a4d08779 |
| 3.7 | 6.12.94 | 4e7c80742e6d |
| 3.7 | 6.18.36 | d4fd42822040 |
| 3.7 | 7.0.13 | 1b47b1e1d867 |
| 3.7 | 7.1.1 | 1268c64e2bcb |
| 3.7 | 7.2 | cfd391e74134 |
Debian advisories
| Advisory | Date | Shipped to | Debian |
|---|---|---|---|
| DLA-4671-1 | 2026-07-05 | bullseye 6.1.176-1~deb11u1 | tracker |
| DLA-4665-1 | 2026-07-03 | bookworm 6.1.176-1 | tracker |
| DLA-4664-1 | 2026-07-03 | bullseye 5.10.259-1 | tracker |
Why the CNA scored it this way
Quoted from the kernel CNA's own scoring file, word for word. A highlighted metric carries the most severe value CVSS v3.1 defines for it, which is what pushes the score up. source
- AV:LAttack vector, local
- The vulnerable TLBI completion path is reachable by locally executing code that drives memory permission/unmap activity through syscalls or guest/KVM memory-management activity. It is not directly exposed by network packets.
- AC:LAttack complexity, low
- Although the erratum depends on timing, the attacker can repeatedly arrange concurrent stores and translation invalidations on affected multicore Arm systems. The triggering race is therefore attacker-influenced rather than dependent on a one-off external condition.
- PR:LPrivileges required, low
- A basic unprivileged local user or guest workload can reach the relevant Stage-1/Stage-2 TLBI paths without host administrative privileges. No real root capability in the init namespace is required.
- UI:NUser interaction, none
- After the attacker has local code execution, exploitation only requires attacker-driven memory operations/syscalls or guest activity. No separate victim action is needed.
- S:CScope, changed
- In a severe reasonable deployment such as Arm KVM/cloud virtualization, bypassing Stage-2 or higher-level translation protections can let guest-controlled writes affect hypervisor/host resources. That crosses a security authority boundary.
- C:HConfidentiality impact, high
- The primitive can enable privilege escalation to kernel or hypervisor context, making protected memory and secrets accessible. Even though the erratum affects stores, successful control of privileged context supports high confidentiality impact.
- I:HIntegrity impact, high
- The core issue permits writes to memory after translation permissions or ownership should have been revoked. This is a high-integrity memory corruption primitive with plausible kernel or hypervisor privilege escalation.
- A:HAvailability impact, high
- Incorrect late writes into protected or reused memory can corrupt kernel/hypervisor state. Failed exploitation or corruption can plausibly cause kernel panic, guest/host crash, or system instability.