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CVE-2026-45894
iommu/vt-d: Clear Present bit before tearing down PASID entry
Published 2026-05-27 (5 months ago) by the Linux kernel CNA. Subsystem drivers/iommu. Debian urgency: not yet assigned.
What to do, per Debian release
Debian's own status for CVE-2026-45894 in every release this site tracks, and what each one means in practice. Every status below is the one the Debian Security Team publishes for this CVE. source
| Release | Status | Version | What this means |
|---|---|---|---|
| Debian 12bookworm | vulnerable | 6.1.190-1 | No fix published anywhere yet, neither in Debian nor upstream for the series bookworm tracks. Watch the Debian tracker page for this CVE. Advisories for bookworm have historically landed a median of 23 days after publication. |
| Debian 13trixie | fixed | 6.12.85-1 | Update the kernel and reboot. Fixed in 6.12.85-1. A running kernel keeps the old code until the machine restarts. |
| Debian 14forky | fixed | 6.18.14-1 | Update the kernel and reboot. Fixed in 6.18.14-1. A running kernel keeps the old code until the machine restarts. |
| Debian unstablesid | fixed | 6.18.14-1 | Update the kernel and reboot. Fixed in 6.18.14-1. A running kernel keeps the old code until the machine restarts. |
The vulnerability
What the bug is
The Intel VT-d Scalable Mode PASID table entry consists of 512 bits (64 bytes). When tearing down an entry, the current implementation zeros the entire 64-byte structure immediately using multiple 64-bit writes. Since the IOMMU hardware may fetch these 64 bytes using multiple internal transactions (e.g., four 128-bit bursts), updating or zeroing the entire entry while it is active (P=1) risks a "torn" read. If a hardware fetch occurs simultaneously with the CPU zeroing the entry, the hardware could observe an inconsistent state, leading to unpredictable behavior or spurious faults. Follow the "Guidance to Software for Invalidations" in the VT-d spec (Section 6.5.3.3) by implementing the recommended ownership handshake: 1. Clear only the 'Present' (P) bit of the PASID entry. 2. Use a dma_wmb() to ensure the cleared bit is visible to hardware before proceeding. 3. Execute the required invalidation sequence (PASID cache, IOTLB, and Device-TLB flush) to ensure the hardware has released all cached references. 4. Only after the flushes are complete, zero out the remaining fields of the PASID entry. Also, add a dma_wmb() in pasid_set_present() to ensure that all other fields of the PASID entry are visible to the hardware before the Present bit is set.
Where it lives
The fix touches these files. If the subsystem is one you do not use, the practical exposure is lower, though the package is still the vulnerable one.
drivers/iommu/intel/pasid.c
drivers/iommu/intel/pasid.h
- What this is
- INTEL IOMMU (VT-d)MAINTAINERS section matched on drivers/iommu/intel/ · iommu@lists.linux.dev · Supported
Check it on the machine
grep -w CONFIG_INTEL_IOMMU /boot/config-$(uname -r)Reads the booted kernel's own configuration, on the machine and nowhere else. =y is built in, =m is a module, and an is not set line means the code is not there.
Show whether Debian builds this, per release
Debian builds this, but not on every flavour. At least one release below builds the code on some of its kernel flavours and not on others, so the answer depends on the architecture and flavour installed.
- bookwormYnot built on arm64/arm64, arm64/cloud-arm64, arm64/rt/arm64, armhf/armmp, armhf/armmp-lpae, armhf/rt/armmp, i386/686, i386/686-pae, i386/rt/686-pae, ppc64el/powerpc64le
- trixieYnot built on arm64/arm64, arm64/arm64-16k, arm64/cloud-arm64, arm64/rt/arm64, armel/rpi, armhf/armmp, armhf/armmp-lpae, armhf/rt/armmp, ppc64el/powerpc64le, ppc64el/powerpc64le-64k, riscv64/riscv64, s390x/s390x
- forky, sidYnot built on arm64/arm64, arm64/arm64-16k, arm64/cloud-arm64, arm64/rt-arm64, armhf/armmp, armhf/armmp-lpae, loong64/loong64, ppc64el/powerpc64le, ppc64el/powerpc64le-64k, riscv64/riscv64, s390x/s390x
- Y
- built in where it is built at all; some flavours do not build it
- Build switch
- CONFIG_INTEL_IOMMU
From the configuration Debian publishes for every kernel flavour it builds. It covers only the architectures Debian ships a linux-config package for, and nothing about a kernel you built yourself. Debian's own status above stays authoritative about the source package.MAINTAINERS kbuild Makefiles Debian linux-config packages
Signals
- Published
- 2026-05-27 (5 months ago)source
- CVSS
- 7.8 high
CVSS:3.1/AV:L/AC:H/PR:L/UI:N/S:C/C:H/I:H/A:Hsource recompute it - Attack vector
- local (AV:L)source
- EPSS
- 0.15%, higher than 3.7% of all CVEssource
- CISA KEV
- not listedthe KEV catalogue
- Debian urgency
- not yet assignedsource
- Subsystem
- drivers/iommu
Upstream fixes
The versions the CNA records as introducing and fixing this, and the commit for each. source
| Introduced | Fixed in | Commit |
|---|---|---|
| 5.0 | 6.12.75 | a84d30e8d2ba |
| 5.0 | 6.18.14 | 821807c167b7 |
| 5.0 | 6.19.4 | 949d71666e9d |
| 5.0 | 7.0 | 75ed00055c05 |
Why the CNA scored it this way
Quoted from the kernel CNA's own scoring file, word for word. A highlighted metric carries the most severe value CVSS v3.1 defines for it, which is what pushes the score up. source
- AV:LAttack vector, local
- The teardown path is reached only through local interfaces — IOMMU domain attach/detach, SVA bind/unbind via accelerator char devices, and VFIO/iommufd ioctls — plus a locally-controlled device's DMA; there is no remote/network path to this code.
- AC:HAttack complexity, high
- Triggering the torn read requires the IOMMU's internal multi-burst fetch of the 64-byte entry to interleave with the CPU's eight 64-bit zeroing writes during the narrow teardown window; this sub-microsecond hardware-internal timing is beyond the attacker's control and cannot be reliably reproduced.
- PR:LPrivileges required, low
- Reaching the teardown requires local access to manage an IOMMU domain or to bind/unbind a PASID on an SVA-capable accelerator (reachable by an unprivileged user granted device access), not a pre-auth or fully unauthenticated path.
- UI:NUser interaction, none
- No victim interaction is needed; the attacker drives both the device DMA and the PASID-entry teardown.
- S:CScope, changed
- The IOMMU enforces the DMA isolation boundary; a torn/inconsistent PASID-entry read can cause the IOMMU to mistranslate a device's DMA, allowing access outside the device's authorized memory scope — an IOMMU/DMA boundary crossing.
- C:HConfidentiality impact, high
- Mistranslation from an inconsistent entry read could let a device (e.g., guest-assigned or SVA-bound) read host physical memory outside its domain, yielding disclosure of memory beyond its authorized scope.
- I:HIntegrity impact, high
- The same mistranslation could let a device perform DMA writes to host physical memory outside its assigned domain, corrupting memory across the isolation boundary.
- A:HAvailability impact, high
- The torn read causes "spurious faults" and "unpredictable" IOMMU behavior, which can produce DMA fault storms or device/translation failures impacting availability.