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CVE-2024-42279

spi: microchip-core: ensure TX and RX FIFOs are empty at start of a transfer

7.8 EPSS 0.2% AV:L

Published 2024-08-17 (2 years ago) by the Linux kernel CNA. Subsystem drivers/spi. Debian urgency: not yet assigned.

What to do, per Debian release

Debian's own status for CVE-2024-42279 in every release this site tracks, and what each one means in practice. Every status below is the one the Debian Security Team publishes for this CVE. source

ReleaseStatus VersionWhat this means
Debian 12bookwormvulnerable6.1.190-1No fix published anywhere yet, neither in Debian nor upstream for the series bookworm tracks. Watch the Debian tracker page for this CVE. Advisories for bookworm have historically landed a median of 23 days after publication.
Debian 13trixiefixed6.10.3-1Update the kernel and reboot. Fixed in 6.10.3-1. A running kernel keeps the old code until the machine restarts.
Debian 14forkyfixed6.10.3-1Update the kernel and reboot. Fixed in 6.10.3-1. A running kernel keeps the old code until the machine restarts.
Debian unstablesidfixed6.10.3-1Update the kernel and reboot. Fixed in 6.10.3-1. A running kernel keeps the old code until the machine restarts.

The vulnerability

What the bug is

While transmitting with rx_len == 0, the RX FIFO is not going to be emptied in the interrupt handler. A subsequent transfer could then read crap from the previous transfer out of the RX FIFO into the start RX buffer. The core provides a register that will empty the RX and TX FIFOs, so do that before each transfer.

Where it lives

The fix touches these files. If the subsystem is one you do not use, the practical exposure is lower, though the package is still the vulnerable one.

drivers/spi/spi-microchip-core.c

What this is
SPI SUBSYSTEMMAINTAINERS section matched on drivers/spi/ · linux-spi@vger.kernel.org · Maintained

Check it on the machine

grep -wE 'CONFIG_SPI|CONFIG_SPI_MICROCHIP_CORE' /boot/config-$(uname -r)

Reads the booted kernel's own configuration, on the machine and nowhere else. =y is built in, =m is a module, and an is not set line means the code is not there.

Show whether Debian builds this, per release

Debian does not build this code in 2 releases. The build rule could not be established for 2 releases, so nothing is claimed about those.

  • bookworm, trixien
  • forky, sid?
n
not enabled on any flavour - this release does not build the code
?
not established - no Makefile entry for the affected file

Where a release above reads "not established", no build rule for the affected file was found in that release's kernel tree. That is a gap in this lookup, not a finding that the code is absent.

Build switches
CONFIG_SPI, CONFIG_SPI_MICROCHIP_CORE
Reads as
all on means the file is compiled; any one off means it is not.

From the configuration Debian publishes for every kernel flavour it builds. It covers only the architectures Debian ships a linux-config package for, and nothing about a kernel you built yourself. Debian's own status above stays authoritative about the source package.MAINTAINERS kbuild Makefiles Debian linux-config packages

Signals

Published
2024-08-17 (2 years ago)source
CVSS
7.8 high
CVSS:3.1/AV:L/AC:L/PR:L/UI:N/S:U/C:H/I:H/A:Hsource recompute it
Attack vector
local (AV:L)source
EPSS
0.23%, higher than 13.3% of all CVEssource
CISA KEV
not listedthe KEV catalogue
Debian urgency
not yet assignedsource
Subsystem
drivers/spi

Upstream fixes

The versions the CNA records as introducing and fixing this, and the commit for each. source

IntroducedFixed inCommit
6.06.6.443feda3677e8b
6.06.10.345e03d35229b
6.06.119cf71eb0faef

Why the CNA scored it this way

Quoted from the kernel CNA's own scoring file, word for word. A highlighted metric carries the most severe value CVSS v3.1 defines for it, which is what pushes the score up. source

AV:LAttack vector, local
The vulnerable `mchp_corespi_transfer_one()` path is entered from the SPI core, reachable locally through spidev ioctls (`SPI_IOC_MESSAGE`) or by driving any in-kernel SPI client; no network or physical access to the board is needed.
AC:LAttack complexity, low
The attacker can reliably dirty the RX FIFO with back-to-back transfers (including transfers larger than the 32-byte FIFO that provoke `INT_RX_CHANNEL_OVERFLOW`, or aborted transfers), and the residue is sticky rather than probabilistic, so no condition outside the attacker's control is required.
PR:LPrivileges required, low
Only ordinary local access to an SPI device node (commonly group-accessible on embedded platforms) or the ability to trigger an SPI client is needed; there is no capability check anywhere on the path from the ioctl to `transfer_one`.
UI:NUser interaction, none
The attacker issues the transfers themselves and the stale-FIFO condition persists on its own; no victim action is required.
S:UScope, unchanged
The impact stays within the kernel and the SPI controller managed by it; no VM, IOMMU, or sandbox boundary is crossed.
C:HConfidentiality impact, high
Bytes clocked in during a previous transaction — from any device on the shared bus, including a TPM, secure element, or the boot/root SPI flash — are copied into the attacker's RX buffer, and the leak can be repeated indefinitely, so security-critical data transiting the bus can be siphoned across driver and process boundaries.
I:HIntegrity impact, high
Residue from the attacker's own transaction is prepended into the next client's `rx_buf`, and an attacker transacting with a readback-capable slave controls those bytes exactly, allowing chosen data to be injected into another driver's input — e.g. corrupting a secure-element/TPM response or data read from the root flash.
A:HAvailability impact, high
The residue count never clears, so once the FIFO fills every subsequent transfer overflows and returns garbage, permanently breaking every device on the controller (rootfs SPI-NOR, watchdog, sensors) until reboot, with SPI core transfer timeouts and `dev_err` spam.